24LC02 DATASHEET PDF

Malalabar Hardware controlled write protection. The device address word consist of a mandatory 42lc02, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address. The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing. Serial clock data input. Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low.

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Malalabar Hardware controlled write protection. The device address word consist of a mandatory 42lc02, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address. The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing. Serial clock data input. Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle.

A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low. Output Valid from Clock. Write satasheet with built-in timer. Internally organized with 8-bit words, the 2K requires an 8-bit data word address for random word addressing. If not, the chip will return to a standby state. Data Input Setup Time. The pin datasheeg open-drain driven and may be wired-OR with any number of other open-drain or open collector devices.

Clock and data transition. A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing.

After receiving the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition. A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word.

Data Input Hold Time. Output Capacitance See Note. Search field Part name Part description. Partial page write allowed. Data transfer may be initiated only when the. For relative timing, refer to timing diagrams. Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput. These are stress ratings only.

These three bits must compare to their corresponding hard-wired input pins. The SDA pin is bidirectional for serial data transfer. After this period the first clock pulse is generated. The microcontroller must terminate the page write sequence with a stop condition. ACK polling can be initiated immediately. The device is optimized for use in many industrial and com. Characteristics Functional Description Timing Diagrams.

Time in which the bus must be free before a new transmission can start. This happens during the ninth clock cycle. During data transfer, the data line must remain stable whenever the clock line is high.

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A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low. If not, the chip will return to a standby state. Write operations A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word.

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